Designing of Full Adder Circuits for Low Power
نویسنده
چکیده
Full adders are important components in applications such as digital signal processing (DSP) architecture, and microprocessors. Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using adiabatic logic style (DTGAL), which are derived from static CMOS logic, without a large change. This paper also proposes a new design of full adder using ULPD (Ultra Low Power Devices) level restorer. The full adders are designed using 0.25μm technology parameters. The different design of full adders is compare on the basis of power dissipation. It is found that, full adders designed with adiabatic logic style and ULPD level restorer tends to consume very low power in comparison to full adder designed with static CMOS logic.
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